1. Field of the Invention
This invention is directed to clock generation circuits, and more particularly to a direct digital phase synthesis circuit and method for generation of a synchronization clock for a telecommunication system.
2. Background Art
In telecommunication systems, the receiver is assumed to be able to generate a set of local clock signals whose phases are identical (except perhaps for a constant offset) to the phases of the signaling alphabet in use at the transmitter. These locally generated signals are compared to the incoming signals in the process of making a maximum likelihood symbol decision. In order to be able to generate these local clock signals, the receiver has to be in synchronization with the received carrier, the beginning of a frame, and the beginning of a symbol of the incoming signal.
For systems using coherent modulation techniques, one direction of communication (such as broadcast channels), or single-link communications (such as most microwave links), the architecture that makes more sense is to make synchronization totally a receiver function. For telecommunication systems that use non-coherent modulation techniques or that involve many users accessing a central communication node, it often makes sense for synchronization to be mostly or entirely a terminal function, with the transmitter assuming a more active role in synchronization. This means that the terminal transmitter parameters are modified rather than modifying the central node's receiver parameters. Synchronization of the system transmitter makes sense with time division multiple access (TDMA) systems, where each user is allocated a segment of time in which to transmit the information, and also with systems that combine signal processing at the central node with frequency division multiple access (FDMA).
In these cases, the transmitter varies the timing and frequency of its transmission to pre-synchronize their transmission with the central node, so that the node can use a fixed set of channel filters and a single timing reference for all channels. Often times, the transmitter relies on a return path from the receiver to determine the accuracy of its synchronization. Without transmitter synchronization, the node will require a separate time and frequency acquisition and tracking capability for each incoming channel, and would need to deal with the possibility of varying amount of adjacent channel interference.
As such, it is known to provide a telecommunication terminal with a master timing generator or a synchronization card, which provides all the above clock signals for synchronization of the receiver and transmitter.
Carrier synchronization is currently obtained using phase locked loops (PLL) which provide an output signal that is of the same frequency and phase with an input signal. As the carrier is a generally a sinusoidal signal, PLLs used for carrier synchronization are analog. The main components of a PLL include a phase detector, a loop filter and a voltage controlled oscillator (VCO), as is well known in the art. The phase detector receives a reference clock extracted from the incoming signal and the local clock, output by the VCO, compares their phases, and provides a control signal for the VCO, which is a measure of the phase difference between these clocks.
For symbol synchronization, the replica generated at the receiver is a square wave at the symbol transition rate. Since there is typically a rather large number of carrier cycles per symbol period, this level of synchronization is much coarser than phase synchronization, and is usually done with other type of circuitry than that used for phase synchronization. Symbol synchronizers can be classified as open loop and closed loop.
In the open loop configurations, the symbol rate is recovered using a combination of filters, a non-linear device, and a high-gain saturated amplifier for shaping the signal to a square wave.
Closed-loop symbol synchronizers use comparative measurements on the incoming signal to bring a locally generated clock signal into synchronism with the incoming data transitions. Among the most popular closed loop symbol synchronizers is the early/late-gate synchronizer, which operates by performing two separate integrations of the incoming signal energy over two different portions of a symbol interval. The early-gate integration begins at the loop's best estimate of the beginning of a symbol period (T) given by the local clock, and integrates over an interval (T-d). The late-gate delays the start of integration for d seconds, and then integrates to the end of the symbol period. The difference between the outputs of these two gates, called the `up` and `down` signals, is a measure of the receiver's symbol timing error, and can be fed back to the local clock to correct loop timing. When in lock, the output signal of the local clock has substantially the same frequency and phase as the reference clock.
Frame synchronization involves creating a square wave at the frame rate with the zero-crossing coincident with the transitions from one frame to the next.
Recently, the analog PLLs have been replaced with digital PLLs (DPLL) for symbol and frame synchronization. DPLLs allow lowering loop bandwidth in order to comply with the communication standards. DPLLs also alleviate some of the problems associated with the analog PLLs, such as for example the sensitivity to DC-drift and the need for calibration and periodic adjustment.
A DPLL can use digital logic circuits, or a specialized digital signal processor (DSP). Current DPLLs are of the first type, being based on direct digital frequency synthesis (DDFS) configurations, or they use a digital phase detector and a digital to analog converter (DAC) for controlling the VCO.
When the PLL uses a DAC, a temperature compensated voltage controlled crystal oscillator (TCVCXO) is necessary. This oscillator is manufactured for a specific frequency, which is generally many times higher than the frequency of the common VCOs, and therefore is expensive. The DAC temperature drift should also be compensated for, which complicates the design. Also, the configurations using DACs often present an unsatisfactory control of the phase drift. This results in phase build-up on the VCO output, which demands for additional circuitry for improving the performance of the PLL.
The direct digital frequency synthesis (DDFS) implies eliminating each n-th pulse in an M-pulses sequence of an incoming digital signal, filtering the resultant signal, eliminating the undesired side bands, and extracting the desired frequency. The circuits based on DDFS are provided with a microcontroller and an EEPROM for determining n, M and effecting the deletion. Also, the DDFS algorithm requires complex logic and long acquisition times. Furthermore, if a low frequency off-shelf oscillator, such as for example a temperature compensated crystal oscillator (TCXO), is used in this configuration, an additional analog PLL is necessary for obtaining the desired high frequency, by multiplying the frequency of the local clock.
Yet another disadvantage of the current DDFS is that the clock has rather high jitters, such that another additional analog PLL is generally used for reducing the jitters.
On the other hand, it is advantageous to use specialized digital signal processors (DSPs) which are less expensive than universal microcontrollers and may be integrated with other circuits on the synchronization card. The DSP can provide the additional hardware if a more complex structure of the DPLL is desired for increasing performance, and is not consuming much of the board's real estate. In addition, modification of the circuit parameters is easy when a DSP is used.
An example of a DPLL using a high performance DSP is provided in the paper entitled "Implemenation of a New Type DSP PLL Using High Performance DSP DSSP-1" by Ono et al., IEEE/IECEJ/ASJ International Conference on Acoustics, Speech and Signal Processing, 1986, pp. 2195-2198. The DPLL has linearity in the phase comparison characteristics, gives fast acquisition times and has a wide pull-in range. However, the DPLL proposed in the article has a complex structure, and in addition it employs an analog to digital converter (A/D) and a digital to analog converters (D/A), which are expensive circuits and inherently add noise to the signal. Such complex configurations are not recommendable for clocks operating at very high frequencies.
Another important parameter to consider when designing synchronizers is the cost. Each level of synchronization that is added to a terminal implies an increase in cost, mostly in the area of acquisition and tracking loops which often times involve not only hardware, but also software costs. Additional costs lie in the extra time required to achieve synchronization before commencing communications, in the energy spent by the transmitter on signals to be used at the receiver as acquisition or tracking aids. These costs increase obviously with the transmission rate and the number of transmission channels, where improved performance and versatility are necessary.
There is a need for a synchronizer and method of synchronization which are cost efficient and applicable to a variety of telecommunication terminals.